1. Field of the Invention
The invention relates to a semiconductor storage device and particularly to an SRAM and the like.
2. Description of the Related Art
In order to lower the power consumption of an LSI, there is a demand of lowering power source voltage. The lower limit of the power source voltage of an LSI is often determined by an SRAM in the LSI. This is due to the disturb problem of a memory cell. Specifically, in a conventional six-transistor memory cell, when a word line is selected for a read operation, a pre-charged bit line is connected to an internal node, which forms a flip-flop circuit, through a transfer transistor, so that the internal node is slightly charged. Accordingly, data of the flip-flop circuit become unstable and data corruption is caused when the power source voltage is lowered. To address such a disturb problem, there is a method in which a selection level of the word line is raised from a non-selective level to a selective level in stages. With this method, when a level of the word line is at an intermediate level, a driving force of a transfer transistor is small, so that an influence of the bit line on the internal node can be suppressed (Document 1: A 1-V TFT-Load SRAM Using Two-Step Word-Voltage Method, Koichiro Ishibashi et. al., IEEE JOURNAL OF SOLID-STAGE CIRCUITS, VOL. 27, No. 11, NOVEMBER 1992).
However, it is difficult to increase the selection level of the word line in stages by a single power source and with a small area overhead. Further, there is a problem that circuit constants have to be adjusted according to a scale of a cell array.